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EP4CGX15BF14A7N ALTERA/INTEL EP4CGX15 Cyclone IV FPGA 72 I/O 169FBGA 3-Gbps 全新原装正品现货

时间:2018-11-01 09:28来源:gongwin.com 作者:省芯商城 点击:
EP4CGX15BF14A7N ALTERA/INTEL Cyclone IV FPGA 72 I/O 169FBGA 3-Gbps 全新原装正品现货
EP4CGX15BF14A7N
ALTERA/INTEL
EP4CGX15
Cyclone IV FPGA 72 I/O 169FBGA 3-Gbps
全新原装正品现货




Altera’s new Cyclone® IV FPGA device family extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs.

Built on an optimized low-power process, the Cyclone IV device family offers the following two variants:
■ Cyclone IV E—lowest power, high functionality with the lowest cost
■ Cyclone IV GX—lowest power and lowest cost FPGAs with 3.125 Gbps transceivers

Providing power and cost savings without sacrificing performance, along with a low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost, small-form-factor applications in the wireless, wireline, broadcast, industrial, consumer, and communications industries.

Cyclone IV Device Family Features
The Cyclone IV device family offers the following features:

■ Low-cost, low-power FPGA fabric:
■ 6K to 150K logic elements
■ Up to 6.3 Mb of embedded memory
■ Up to 360 18 × 18 multipliers for DSP processing intensive applications
■ Protocol bridging applications for under 1.5 W total power

Cyclone IV GX devices offer up to eight high-speed transceivers that provide:
■ Data rates up to 3.125 Gbps
■ 8B/10B encoder/decoder
■ 8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface
■ Byte serializer/deserializer (SERDES)
■ Word aligner
■ Rate matching FIFO
■ TX bit slipper for Common Public Radio Interface (CPRI)
■ Electrical idle
■ Dynamic channel reconfiguration allowing you to change data rates and protocols on-the-fly
■ Static equalization and pre-emphasis for superior signal integrity
■ 150 mW per channel power consumption
■ Flexible clocking structure to support multiple protocols in a single transceiver block

更多资料请参考:
http://www.mouser.cn/datasheet/2/612/cyiv-51001-1299459.pdf


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