H5RS5223CFR-11C HYNIX说明512Mbit (16Mx32) GDDR3 SDRAM• 2.05V/ 1.8V/ 1.5V power supply supports (For more detail, Please see the Table 12 on page 43) • Single ended READ Strobe (RDQS) per byte • Single ended WRITE Strobe (WDQS) per byte • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle •On Die Termination • Output Driver Strength adjustment by EMRS • Calibrated output driver • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • RDQS edge-aligned with data for READ; with WDQS center-aligned with data for WRITE • 8 internal banks for concurrent operation  H5RS5223CFR-11C HYNIX现货订购热线： 电话： 0755-8278 2277 手机： 13823737353 传真： 0755-83138727 Email：ryan#gongwin.com QQ： (责任编辑：www.gongwin.com) |
