PLL500-17TCL PhaseLink说明Low Phase Noise VCXO (17MHz to 36MHz)• VCXO output for the 17MHz to 36MHz range • Low phase noise (-130 dBc @ 10kHz offset at 35.328MHz). • CMOS output with OE tri-state control. • 17 to 36MHz fundamental crystal input. • Integrated high linearity variable capacitors. • 12mA drive capability at TTL output. • +/- 150 ppm pull range, max 5% (typ.) linearity. • Low jitter (RMS): 2.5ps period jitter. • 2.5 to 3.3V operation. • Available in 8-Pin SOIC, 6-pin SOT23 GREEN/ RoHS compliant packages, or DIE.  PLL500-17TCL PhaseLink现货订购热线： 电话： 0755-8278 2277 手机： 13823737353 传真： 0755-83138727 Email：ryan#gongwin.com QQ： (责任编辑：www.gongwin.com) |
